Technological Field
The disclosed technology relates to the semiconductor technology, and particularly to N-type MOSFETs, including a metal gate layer and a high-k gate dielectric layer, and methods for manufacturing the same.
Description of the Related Technology
As semiconductor technology advances, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) feature sizes are decreasing. The decrease in size of the MOSFETs causes a significant problem of gate current leakage. The gate leakage current can be reduced by using a high-k gate dielectric layer, which may have an increased physical thickness with respect to a given equivalent oxide thickness (EOT). Unfortunately, a conventional Poly-Si gate is incompatible with the high-k gate dielectric layer. By using a combination of a metal gate layer and the high-k gate dielectric layer, it is possible not only to avoid the depletion effect of the Poly-Si gate and decrease gate resistance, but also to avoid boron penetration and enhance device reliability. Therefore, the combination of the metal gate layer and the high-k gate dielectric layer is widely used in the MOSFETs. However, integrating the metal gate layer and the high-k gate dielectric layer presents many challenges including thermal stability and interfacial states. In particular, it is difficult for MOSFETs using the metal gate layer and the high-k gate dielectric layer to have an adequately low threshold voltage due to the Fermi-Pinning Effect.
To obtain an appropriate threshold voltage, an N-type MOSFET should have its effective work function near the bottom of the conduction band of Si (about 4.1 eV). One approach is to select an appropriate combination of a metal gate layer and a high-K gate dielectric layer for the N-type MOSFET, so as to achieve the desired threshold voltage. However, it is difficult to obtain such a low effective work function simply by altering materials.